The invention relates generally to chemical vapor deposition systems, and more particularly to rapid thermal processing (RTP) systems.
Chemical vapor processes for thin film fabrication pass a vapor over a substrate to either grow a film on the substrate, etch the substrate, or otherwise react with a material on the substrate to change the character of the substrate surface. The types of substrates referred to here include wafers for ultra-large scale integrated (ULSI) circuits. The substrate is sometimes subjected to RTP to facilitate or speed vapor processing while minimizing handling. RTP refers to several different processes, including rapid thermal annealing (RTA), rapid thermal cleaning (RTC), rapid thermal chemical vapor deposition (RTCVD), rapid thermal oxidation (RTO), and rapid thermal nitridation (RTN).
In one RTP process, wafers are loaded into a processing chamber at room temperature to several hundred degrees Celsius in a nitrogen (N.sub.2) gas ambient atmosphere. The temperature of the wafer is ramped to a process temperature, usually in the range of about 600.degree. C. to 1200.degree. C. The temperature is raised using a large number of halogen lamps which radiatively heat the wafer. The temperature stabilizes over a pre-set time period, and reactive gases are introduced. The gas may be introduced while ramping the temperature. For example, oxygen may be introduced for growing a layer of silicon dioxide (SiO.sub.2).
The wafer is sometimes supported around the periphery of its bottom side on an annular-shaped ledge of a supporting edge ring. The wafer's peripheral edge is left exposed. Gaseous products of the chemical reactions on the wafer are expected to be exhausted via a pumping system. In such a system, the reactive gases can spill over the edge of the wafer and edge ring, or may leak to the region below the wafer due to imperfections in the edge ring supporting the wafer or due to incomplete coverage of the edge ring by the wafer. The spilled-over process gasses can deposit a non-uniform film on the peripheral edge of the wafer, on its backside, or on components located below the wafer. The presence of hot gases in these regions can also cause damage and corrosion. Accumulated deposits may also flake off, contaminating the process chamber with particles. Also, non-uniform depositions around the edge of the wafer are undesirable for subsequent wafer processing.
One approach to inhibit the process gases from depositing on the edge or backside is to use an edge ring that covers a portion of the upper surface of the wafer. Another approach is to coat the entire backside of the wafer uniformly to produce a more stable film less likely to flake. To this end, the wafer is supported on pins so that the process gases can easily deposit on the backside.
In those cases where depositing on the backside is undesirable, one or another of a variety of edge-specific purges with inert gases are used to prevent reactive gases from reaching the edge and backside areas. One type of such a system uses a susceptor with built-in channels for directing purge gas flows to the edge of the wafer.
Current schemes for providing effective edge purging may incompletely isolate the backside from reactive gases if the flow of purge gas is too weak. If the purge gas is flowed more strongly, it can spill over the front side of the wafer and mix with the process gas at the periphery of the wafer by diffusion or by convection. The resulting dilution of reactive gases over the front side of the wafer leads to incomplete film deposition near the periphery of the front side, thereby reducing the usable area having a uniform film on the wafer.
The uniformity of the process over the surface of the substrate during thermal processing is also critical to producing uniform devices. For example, in the particular application of complementary metal-oxide-semiconductor (CMOS) gate dielectric formation by RTO or RTN, thickness, growth temperature, and uniformity of the gate dielectrics are critical parameters that influence the overall device performance and fabrication yield. Currently, CMOS devices are being made with dielectric layers that are only 60-80 Angstroms (10.sup.-10 m) thick and for which thickness uniformity must be held within .+-.2 .ANG.. This level of uniformity requires that temperature variations across the substrate during high temperature processing cannot exceed a few degrees Celsius. Temperature uniformity provides uniform process variables on the substrate (e.g., layer thickness, resistivity, etch depth) for process steps including film deposition, oxide growth and etching. In addition, temperature uniformity across the substrate is necessary to prevent thermal stress-induced wafer damage such as warpage, defect generation and slip. This type of thermal stress is caused by thermal gradients which are minimized by temperature uniformity. The wafer often cannot tolerate even small temperature differentials during high temperature processing. Therefore, any viable purge scheme should not adversely affect temperature uniformity during processing.